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april 2010 doc id 17127 rev 1 1/15 15 L6747C high current mosfet driver features dual mosfet driver for synchronous rectified converters high driving current for fast external mosfet switching high frequency operation enable pin adaptive dead-time management flexible gate-drive: 5 v to 12 v compatible high-impedance (hiz) management for output stage shutdown preliminary overvoltage (ov) protection vfdfpn8 3x3 mm package applications high current vrm / vrd for desktop / server / workstation cpus high current and high efficiency dc-dc converters description the L6747C is a flexible, high-frequency dual- driver specifically designed to drive n-channel mosfets connected in synchronous-rectified buck topology. combined with st pwm controllers, the driver allows the implementation of complete voltage regulator solutions for modern high-current cpus and for dc-dc conversion in general. the L6747C embeds high-current drivers for both high-side and low-side mosfets. the device accepts a flexible power supply of 5 v to 12 v. this allows optimization of the high-side and low- side gate-drive voltage to maximize system efficiency. anti shoot-through management prevents the high-side and low-side mosfets from conducting simultaneously and, combined with adaptive dead-time control, minimizes the ls body diode conduction time. the L6747C features preliminary ov protection to protect the load from dangerous overvoltage due to mosfet failures at startup. the driver is available in a vfdfpn8 3x3 mm package. vfdfpn8 3x3 mm table 1. device summary order codes package packing L6747C vfdfpn8 tube L6747Ctr vfdfpn8 tape and reel www.st.com
contents L6747C 2/15 doc id 17127 rev 1 contents 1 typical application cir cuit and block diagram . . . . . . . . . . . . . . . . . . . . 3 2 pin information and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 high-impedance (hiz) management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 preliminary ov protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 boot capacitance design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
L6747C typical application circuit and block diagram doc id 17127 rev 1 3/15 1 typical application circuit and block diagram figure 1. L6747C typical application circuit figure 2. L6747C block diagram boot ugate pha s e lgate h s l s v in = 5v to 12v l c out vo u t c hf c bulk c dec gnd pwm v cc = 5v to 12v L6747C reference s chem a tic L6747C vcc pwm inp u t en en inp u t vcc boot lgate ugate gnd adaptive anti cro ss conduction h s l s vcc pwm pha s e control logic & protection s L6747C pwm en 70k 7k 10k 10k
pin information and thermal data L6747C 4/15 doc id 17127 rev 1 2 pin information and thermal data 2.1 pin information figure 3. pin connection diagram (top view) table 2. pin descriptions pin # name function 1boot high-side driver supply. this pin supplies the high-side floating driver. connect through a r boot - c boot (2.2 - 220nf typ.) network to the phase pin. see section 4.3 for guidance in designing the capacitor value. 2pwm control input for the driver; 5v compatible, internally clamp to 3.3v. this pin controls the state of the driv er and which external mosfet must be turned on according to en status. if manages the high-impedance (hiz) st ate which sets all the mosfets to off if externally set in the hiz window (see ta b l e 5 ). see section 4.1 for details of hiz. 3en enable input for the driver; 5v compatible, internally clamp to 3.3v. pull high to enable the driver based on the pwm status. pull low to enter hiz state with all mosfet off, regardless of the pwm status. see section 4.1 for details of hiz. 4vcc device and ls driver power supply. connect to any voltage between 5v and 12v. bypass with low-esr mlcc capacitor to gnd (1 f typ). 5lgate low-side driver output. connect directly to the low-side mosfet gate. a small series resistor may be used to reduce dissipated power especially in high frequency applications. 6gnd all internal references, logic and drivers are referenced to this pin. connect to the pcb ground plane. 7 phase high-side driver return path. connect to the high-side mosfet source. this pin is also monitored for adapt ive dead-time management and pre-ov protection. internal clamp circuitry prevent leakage from this pin in disable conditions. 1 2 3 4 lgate gnd pha s e ugate vcc en pwm boot 5 6 7 8 L6747C
L6747C pin information and thermal data doc id 17127 rev 1 5/15 2.2 thermal data table 3. thermal data 8ugate high-side driver output. connect to high-side mosfet gate. a small series resistor may be used to control the phase pin negative spike. -th. pad thermal pad connects the silicon substr ate and makes good thermal contact with the pcb. connect to the pgnd plane. table 2. pin descriptions (continued) pin # name function symbol parameter value unit r thja thermal resistance junction-to-ambient (device soldered on 2s2p, 67mm x 69mm board) 45 c/w r thjc thermal resistance junction-to-case 5 c/w t max maximum junction temperature 150 c t stg storage temperature range 0 to 150 c t j junction temperature range 0 to 125 c p tot maximum power dissipation at 25c (device soldered on 2s2p,67mm x 69mm board) 2.25 w
electrical specifications L6747C 6/15 doc id 17127 rev 1 3 electrical specifications 3.1 absolute maximum ratings table 4. absolute maximum ratings 3.2 electrical characteristics v cc = 12 v15%, t j = 0 c to 70 c unless otherwise specified. symbol parameter value unit v cc to gnd -0.3 to 20 v v boot to gnd to gnd, t < 200 ns to phase -0.3 to 41 -0.3 to 44 -0.3 to 15 v v ugate t < 200 ns phase -0.3 to boot +0.3 phase -1 to boot +0.3 v v phase to gnd to gnd; t < 200 ns, vcc = 12v -8 to 26 -8 to 30 v v lgate to gnd to gnd, t < 200 ns -0.3 to vcc + 0.3 -1.5 to vcc + 0.3 v v pwm, v en to gnd -0.3 to 7 v table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit supply current and power-on i cc vcc supply current ugate = lgate = open; boot = 12v; en = 1; pwm = 1 1.5 2.0 ma ugate = lgate = open; boot = 12v; en = 1; pwm = 0 2.7 3.5 ma ugate = lgate = open; boot = 12v; en = 0 1.0 1.5 ma i boot boot supply current ugate = open; phase = gnd; boot = 12v; en = 1; pwm = 1 2.3 3.3 ma ugate = open; phase = gnd; boot = 12v; en = 1; pwm = 0 2.0 3.0 ma ugate = open; phase = gnd; boot = 12v; en = 0 1.3 2.3 ma uvlo vcc vcc turn-on vcc rising 4.1 v vcc turn-off vcc falling 3.5 v
L6747C electrical specifications doc id 17127 rev 1 7/15 pwm and en input pwm input high - v pwm_ih pwm rising 2 v input low - v pwm_il pwm falling 0.8 v input leakage pwm = gnd -5 5 a t hiz hiz hold-off time see figure 4 120 ns t prop_l propagation delays see figure 4 25 35 ns t prop_h 30 45 ns en input high - v en_ih en rising 2 v input low - v en_ih en falling 0.8 v gate drivers r hihs hs source resistance boot - phase = 12v; 100ma 1.4 2.0 i ugate hs source current (1) boot - phase = 12v; c ugate to phase = 3.3nf 3.5 a r lohs hs sink resistance boot - phase = 12v; 100ma 1.0 1.5 r hils ls source resistance 100ma 1.4 2.0 i lgate ls source current (1) c lgate to gnd = 5.6nf 3.5 a r lols ls sink resistance 100ma 1.0 1.5 protections v pre_ov pre-ov threshold phase rising 1.7 1.8 v 1. parameter(s) guaranteed by design, not fully tested in production table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
device description and operation L6747C 8/15 doc id 17127 rev 1 4 device description and operation the L6747C provides high-current driving control for both high-side and low-side n-channel mosfets, connected as step-down dc-dc converters and driven by an external pwm signal. the integrated high-current drivers allow the use of different types of power mosfets (also multiple mos to reduce the equivalent r ds(on) ), maintaining fast switching transition. the driver for the high-side mosfet uses the boot pin for supply and the phase pin for return. the driver for the low-si de mosfet uses the vc c pin for supply and the pgnd pin for return. the driver includes anti-shoot-through and adaptive dead-time control to minimize low-side body diode conduction time, maintaining good efficiency and eliminating the need for schottky diodes. when the high-side mosfet turns off, the voltage on its source begins to fall; when the voltage falls below the proper threshold, the low-side mosfet gate drive voltage is suddenly applied. when the low-side mosfet turns off, the voltage at the lgate pin is sensed. when it drops below the proper threshold, the high-side mosfet gate drive voltage is suddenly applied. if the current flowing in the inductor is negative, the source of the high-side mosfet never drops. to allow the low-side mosfet to turn on even in this case, a watchdog controller is enabled. if the source of the high-side mosfet does not drop, the low-side mosfet is switched on, allowing the negative current of the inductor to recirculate. this mechanism allows the system to regulate even if the current is negative. before v cc goes above the uvlo threshold, the L6747C keeps both the high-side and low- side mosfets firmly off. then, after the uvlo has been crossed, the en and pwm inputs take control over the driver?s operations. the en pin enables the driver. if low, it keeps all mosfets off (hiz) regardless of the status of pwm. when en is high, the pwm input takes control. if externally set within the hiz window, the driver enters an hiz state and both mosfets are kept in an off state until pwm exits the hiz window (see figure 4 ). after the uvlo threshold has been crossed and while in hiz, the preliminary ov protection is activated. if the voltage sensed through the phase pin goes above about 1.8 v, the low- side mosfet is latched on in order to protect the load from dangerous overvoltage. the driver status is reset from a pwm transition. driver power supply, as well as power conversion input, are flexible: 5 v and 12 v can be chosen for high-side and low-side mosfet voltage drive. figure 4. timing diagram (en = high) t prop_l t prop_h t dead_lh t dead_hl t prop_ l t hold-off hiz window pwm hs gate ls gate hiz window hiz t hold-off hiz t prop_ h v pwm_ih v pwm_il
L6747C device description and operation doc id 17127 rev 1 9/15 4.1 high-impedance (hiz) management the driver is capable of managing a high-impedance conditions by keeping all mosfets in an off state. this is achieved in two different ways: if the en signal is pulled low, the device keeps all mosfets off regardless of the pwm status. when en is asserted, if the pwm signal is externally set within the hiz window for a time greater than the hold-off time, the device detects the hiz condition and turns off all the mosfets. the hiz window is defined as the pwm voltage range between v pwm_hiz_h = 1.6 v and v pwm_hiz_l = 1.3 v. the device exits from the hiz state after any pwm transition. see figure 4 for details about hiz timing. the implementation of the high-impedance state allows the controller connected to the driver to manage the high-impedance state of its output, preventing the generation of nega- tive undershoot on the regulated voltage during the shutdown stage. also, different power management states may be managed, such as pre-bias startup. 4.2 preliminary ov protection when v cc exceeds its uvlo threshold while the device is in hiz, the L6747C activates the preliminary ov protection. the intent of this protection feature is to protect the load during system startup, especially from high-side mosfet failures. in fact, vrm, and more generally pwm, controllers, have a 12 v bus-compatible turn-on threshold and are non-operative if v cc is below the turn-on thresholds (which is in the range of about 10 v). in cases of high-side mosfet failure, the controller does not recognize the overvoltage until v cc = ~10 v (unless other special fea- tures are implemented). however, in this case the output voltage is already at the same volt- age (~10 v) and the load (a cpu in most cases) is already burnt. the L6747C bypasses the pwm controller by latching on the low-side mosfet if the phase pin voltage exceeds 2 v during the hiz state. when the pwm input exits from the hiz window, the protection is reset and the control of the output voltage is transferred to the controller connected to the pwm input. since the driver has its own uvlo threshold, a simple way to provide protection to the out- put in all conditions when the device is off is to supply the controller through the 5 v sb bus. 5 v sb is always present before any other voltage and, in case of high-side short, the low- side mosfet is driven with 5 v. this ensures reliable protection of the load. preliminary ov is active after uv lo and while the driver is in an hiz state, and it is disabled after the first pwm transition. the controller must manage its output voltage from that moment on. 4.3 boot capacitance design the bootstrap capacitor value should be selected to obtain a negligible discharge due to the turning on of the high-side mosfet. it must provide a stable voltage supply to the high-side driver during the mosfet turn-on, and minimize the power dissipated by the embedded boot diode. figure 5 illustrates some guidelines on how to select the capacitance value for the bootstrap according to the desired discharge, and the selected mosfet.
device description and operation L6747C 10/15 doc id 17127 rev 1 to prevent the bootstrap capacitor from over charging as a consequence of large negative spikes, an external series r boot resistor (in the range of few ohms) may be required in series with the boot pin. figure 5. bootstrap capacitance design 4.4 power dissipation the L6747C embeds high current drivers for both high-side and low-side mosfets. it is therefore important to consider the power that the device is going to dissipate in driving them in order to avoid exceeding the maximum junction operating temperature. two main factors contribute to device power dissipation: bias power and driver power. device power (p dc ) depends on the static consumption of the device through the supply pins and is easily quantifiable as follows: driver power is the power needed by the driver to continuously switch the external mosfets on and off. it is a function of the switching frequency and total gate charge of the selected mosfets. it can be quantified considering that the total power p sw dissipated to switch the mosfets is influenced by three main factors: external gate resistance (when present), intrinsic mosfet resistance, and intrinsic driver resistance. this last factor is the important one to be determined to calculate the device power dissipation. the total power dissipated to switch the mosfets is: when designing an application based on the L6747C it is recommended to take into consideration the effect of external gate resistors on the power dissipated by the driver. external gate resistors help the device to dissipate the switching power since the same power p sw is shared between the internal driver impedance and the external resistor, resulting in a general cooling of the device. referring to figure 6 , a classic mosfet driver can be represented by a push-pull output stage with two different mosfets: a p-mosfet to drive the external gate high, and an n- mosfet to drive the external gate low (with their own r ds(on) : r hi_hs, r lo_hs , r hi_ls, r lo_ls ). the external power mosfet can be represented in this case as a capacitance (c g_hs , c g_ls ) that stores the gate-charge (q g_hs , q g_ls ) required by the external power 0.0 0.5 1.0 1.5 2.0 2.5 0 102030405060708090100 high-side mosfet gate charge [nc] boot cap discharge [v] cboot = 47nf cboot = 100nf cboot = 220nf cboot = 330nf cboot = 470nf 0 500 1000 1500 2000 2500 0.0 0.2 0.4 0.6 0.8 1.0 boot cap delta voltage [v] bootstrap cap [uf] qg = 10nc qg = 25nc qg = 50nc qg = 100nc p dc v cc i cc v pvcc i pvcc ? + ? = p sw f sw q ghs pvcc ? q gls vcc ? + () ? =
L6747C device description and operation doc id 17127 rev 1 11/15 mosfet to reach the driving voltage (pvcc for hs and vcc for ls). this capacitor is charged and discharged at the driver switching frequency f sw . the total power p sw is dissipated among the resistive components distributed along the driving path. according to the external gate resistance and the power mosfet intrinsic gate resistance, the driver dissipates only a portion of p sw as follows: the total power dissipated from the driver can then be determined as follows: figure 6. equivalent circuit for a mosfet driver 4.5 layout guidelines L6747C provides drivi ng capability to implement high-cur rent step-down dc-dc converters. the first priority when placing components for these applications should be given to the power section, minimizing the length of each connection and loop as much as possible. to minimize noise and voltage spikes (as well as emi and losses) power connections must be part of a power plane, and in any case constructed with wide and thick copper traces. the loop must be minimized. the critical components, such as the power mosfets, must be close to each other. however, some space between the power mosfets is required to assure good thermal cooling and airflow. traces between the driver and the mosfets should be short and wide to minimize the inductance of the trace, which in turn minimizes ringing in the driving signals. moreover, the via count should be minimized to reduce the related parasitic effect. the use of a multi-layer printed circuit board is recommended. small signal components and connections to critical nodes of the application, as well as bypass capacitors for the device supply, are also important. place the bypass capacitor p sw hs ? 1 2 -- - c ghs pvcc 2 fsw r hihs r hihs r gatehs r ihs ++ --------------------------------------------------------------- - r lohs r lohs r gatehs r ihs ++ --------------------------------------------------------------- - + ?? ?? ?? ?? = p sw ls ? 1 2 -- - c gls vcc 2 fsw r hils r hils r gatels r ils ++ ------------------------------------------------------------- - r lols r lols r gatels r ils ++ ------------------------------------------------------------- - + ?? ?? ?? ?? = pp dc p sw hs ? p sw ls ? ++ = r gatels r ils c gls vcc ls driver ls mosfet gnd lgate r gatehs r ihs c ghs boot hs driver hs mosfet phase hgate vcc r hils r lols r hihs r lohs
device description and operation L6747C 12/15 doc id 17127 rev 1 (vcc, pvcc and boot capacitors) close to the device with the shortest possible loop, using wide copper traces to minimize parasitic inductance. systems that do not use schottky diodes in parallel with the low-side mosfet might show large negative spikes on the phase pin. this sp ike can be limited, as can the positive spike, but has an additional consequence: it caus es the bootstrap capacitor to be overcharged. this extra charge can cause, in the worst case condition of maximum input voltage and during particular transients, that boot-to- phase voltage exceeds the absolute maximum ratings causing device failures. it is therefore suggested in this cases to limit this extra charge by adding a small r boot resistor in series with the boot capacitor. the use of r boot also contributes in the limitation of the spike present on the boot pin. for heat dissipation, place the copper area under the ic. this copper area may be connected by internal copper layers through several vias to improve thermal conductivity. the combination of copper pad, copper plane and vias under the driver allows the device to achieve its best thermal performance. figure 7. driver turn-on and turn-off paths figure 8. external component placement example r gate r int c gd c gs c ds vcc ls driver ls mosfet gnd lgate r gate r int c gd c gs c ds boot hs driver hs mosfet phase hgate vcc r boot c boot r boot c boot r b oot c b oot 1 2 3 4 lgate gnd pha s e ugate vcc en pwm boot 5 6 7 8 L6747C d c
L6747C package mechanical data doc id 17127 rev 1 13/15 5 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 9. vfdfpn8 mechanical data and package dimensions dimensions ref. mm mils min. typ. max. min. typ. max. a 0.80 0.90 1.00 31.49 35.43 39.37 a1 0.02 0.05 0.787 1.968 a2 0.65 25.59 a3 0.20 7.874 b 0.18 0.25 0.30 7.086 9.842 11.81 d 3.00 118.1 d2 2.20 2.70 86.61 106.3 e 3.00 e2 1.40 1.75 55.11 68.89 e0.50 l 0.30 0.40 0.50 11.81 15.74 19.68 package and packing information vfdfpn8 (3x3) weight: not available very thin fine pitch dual flat package no lead 0.55 0.80 2.85 3.15 2.85 3.15 ddd 0.08 3.149 21.65 31.49 112.2 124.0 118.1 112.2 124.0 19.68
revision history L6747C 14/15 doc id 17127 rev 1 6 revision history table 6. document revision history date revision changes 23-apr-2010 1 initial release.
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